The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device, which includes a clock tree circuit for correcting the duty cycle of a clock.
As is generally known in the art, a semiconductor memory device uses a delay-locked loop in order to compensate for a skew between an external clock and data, or between an external clock and an internal clock.
Also, in order to correct the duty cycle of a clock delay-locked in a delay-locked loop, a clock tree circuit as shown in FIG. 1 is used. The clock tree circuit has a construction as shown in FIG. 1, and is constituted between the delay-locked loop and a read data path, which includes a latch, an output buffer, etc.
Generally, a clock tree circuit 20 includes a plurality of inverters “INV1” which are serially connected. In addition, the clock tree circuit 20 includes multiple pairs of pull-up and pull-down elements “PM1” and “NM1”, respectively, each pair of which is connected between the inverters “INV1” in order to correct the duty cycle of a clock, in which each of the pull-up and pull-down elements has a beta ratio based on a set state of a metal option 21.
According to the clock tree circuit 20 of FIG. 1, the duty cycle of a delay-locked loop (DLL) clock “DLL_CLK” outputted by the delay-locked loop 10 is corrected based on an initial set of a beta ratio, and then an output clock “CLK_OUT” is measured. Then, when it is determined as a result of the measurement that the duty cycle of the output clock has not been corrected to a ratio desired by the designer, the beta ratio is adjusted, and such measurement and adjustment are repeated, thereby correcting the duty cycle of the output clock “CLK_OUT”.
However, such a conventional clock tree circuit has a problem in that it is impossible to determine whether a distortion in the duty cycle of a measured output clock “CLK_OUT” is caused by the delay-locked loop or by the clock tree circuit itself.
That is, the duty cycle of the clock “CLK_OUT” output from a clock tree circuit may be influenced by the delay-locked loop or by the beta ratio set in the clock tree circuit. A duty cycle distortion caused by the clock tree circuit can be corrected by adjusting the beta ratio of an internal inverter in the clock tree circuit. However, it is difficult to correct a duty cycle distortion caused by the delay-locked loop, and such a correction requires a lot of time and resources.
Additionally, since the conventional clock tree circuit adjusts a duty cycle by using a metal option, it takes a lot of time to correct a duty cycle, thereby delaying the time schedule for development thereof.